Hereinafter, a conventional synthesizer is described with reference to FIG. 6. FIG. 6 is a block diagram of a conventional synthesizer. In FIG. 6, synthesizer 60 has: phase comparator 61 that outputs a pulse width signal proportional to a phase difference between a reference oscillation signal outputted from reference oscillator 69 and a comparison signal outputted from later-mentioned frequency divider 64; loop filter 62 that receives the pulse width signal and outputs a low-pass filtered signal; VCO 63 that outputs an oscillation signal based on the low-pass filtered signal; and frequency divider 64 that divides the oscillation signal based on a frequency division ratio set by later-mentioned control unit 68, and outputs a comparison signal. These constitute a phase locked loop (hereinafter referred to as “PLL”).
Further, synthesizer 60 has: temperature detecting unit 65 that detects an ambient temperature of reference oscillator 69; AD converter 66 that converts the detected temperature to digitalized temperature information; nonvolatile memory 67 that stores frequency division ratio information corresponding to the temperature information; and control unit 68 that sets a frequency division ratio of frequency divider 64 based on the frequency division ratio information.
With such a configuration, even when a frequency of the reference oscillation signal changes depending on the ambient temperature of reference oscillator 69, it is possible to perform control (hereinafter referred to as “frequency compensation control”) to hold an oscillation signal, outputted from synthesizer 60, at a fixed value. In the PLL included in synthesizer 60, when the frequency of the reference oscillation signal is Fref and the frequency division ratio is M, frequency Fvco of the oscillation signal outputted from synthesizer 60 is expressed by (Equation 1):Fvco=Fref×M  (Equation 1)
Herein, Fref is a function of temperature. By means of this relation, when the ambient temperature of reference oscillator 69 changes to cause an increase in Fref by “a” times, M is set to 1/a times so that Fvco can be held at a fixed value despite the change in temperature. Therefore, the frequency compensation control can be performed in such a manner that a combination table for frequency division ratio M, intended to make the ambient temperature of reference oscillator 69 and Fvco fixed values, is previously written into nonvolatile memory 67, and frequency division ratio M read from nonvolatile memory 67 corresponding to a temperature detected by temperature detecting unit 65 is set into frequency divider 64 by control unit 68. As for prior art document information relative to the invention of this application, for example, Patent Document 1 is known.
However, in the above conventional controlling method, the oscillation signal outputted from synthesizer 60 may generate a frequency variation width not smaller than a predetermined value, to have an adverse effect on processing by a signal processing unit (not shown) connected to a subsequent stage to synthesizer 60.